Researchers at the Indian Institute of Technology (IIT) Delhi have developed India’s first working and demonstrable indigenous micro-Graphics Processing Unit (GPU), marking a major step towards reducing the country’s dependence on imported GPU technology. Officials said the development could support the creation of locally designed graphics and display-processing systems for several embedded applications.

GPUs are widely used in modern computing systems, including artificial intelligence (AI) and machine learning platforms. India currently imports all of its GPUs. The new micro-GPU developed by IIT Delhi researchers offers an indigenous architecture that can be used for graphics and display processing in affordable embedded systems.

IIT-Delhi’s Electrical Engineering department research team demonstrated programmable graphics rendering using a custom floating-point GPU engine. The processor was developed entirely in Register Transfer Language (RTL) and implemented on a Spartan-7 Field-Programmable Gate Array (FPGA) platform.

The architecture is designed as a scalable and programmable graphics processor intellectual property (IP). It can support applications such as industrial control displays, low-cost human-machine interfaces, e-rickshaw dashboard navigators, inland-water navigation terminals for small fishing boats and educational e-book readers.

Explaining the objective of the project, MTech student Nammi Akash said, "The hardware architecture is a scalable programmable graphics processor IP suitable for applications such as industrial control displays, low-cost human-machine interfaces, e-rickshaw dashboard navigators, inland-water navigation terminals for small fishing boats, educational e-book readers, and other affordable embedded visualisation systems. It may be mapped to silicon ASIC or programmable hardware such as FPGAs. Our objective was to create a compact but genuinely programmable graphics-processing architecture suitable for FPGA implementation and future ASIC realisation”.

"We hope such indigenous hardware systems can support affordable digital-access platforms and contribute meaningfully toward bridging the digital divide," he added.

The researchers are now working on the next stage of the project. Their roadmap includes developing an 8-16 core vector-style graphics processor architecture. The team also plans to build an optimised compiler and graphics software toolchain.

The researchers eventually aim to move towards a proof of concept using a 65nm ASIC process node. They believe mature semiconductor technologies such as 65nm could help make indigenous graphics silicon economically viable for embedded applications.

Kaushik Saha, Professor in the Electrical Engineering department, said the project also allows students to work across multiple areas of hardware development. The project brings together arithmetic hardware, programmable architectures, compilers and embedded systems within a single framework. It also focuses on wider challenges related to affordable digital access.